The present invention relates to integrated circuit modules and, in particular, to standby control circuits for activating a standby mode in which a secondary power supply provides power to the integrated circuit module.
Integrated circuits modules are commonly designed with a reduced power operating mode (or an “idle mode”) in which selected functional blocks of the integrated circuit module are disabled to reduce static power consumption during periods of little or no activity. A reduced power operating mode may provide an appreciable reduction in static power consumption, particularly in cases where power intensive functional blocks, such as clock generation circuits (such as a phase locked loop), are disabled. In some integrated circuit designs the disabled functional blocks may include a clock generation circuit that generates, in a normal operating mode of the integrated circuit module, a System Clock signal for the integrated circuit module. Hence, in the reduced power operating mode the System Clock may be inactive, and thus not available.
In addition to the normal operating mode and the reduced power operating mode, an integrated circuit module may also be designed to provide a “standby operating mode” that is “entered” in response to activation of a standby signal, which is typically an asynchronous signal.
In the standby mode, a power supply voltage from a primary power supply (such as a 3.3V power supply) may be isolated from all but essential functional blocks required to restore the integrated circuit module to the normal operating mode. In the standby mode, the essential functional blocks may be powered by a secondary power supply, such as a battery, which provides a secondary power supply voltage. In such a case it is important that the load on the battery be minimized to preserve battery life.
In some integrated circuit designs, “entry” into standby mode is managed by a standby control circuit on-board the integrated circuit module. One example of an on-board standby control circuit 100 is shown in FIG. 1. In this example, the asynchronous standby signal 102 is provided to an input of an edge triggered register 104. A clock signal 103 (SYSTEM CLOCK) is provided to a clock input of the register 104 to propagate the asynchronous standby signal 102 to the output 106 of the register 104 synchronous with an edge of the clock signal. An AND 110 gate receives the data output 106 and passes the SYSTEM CLOCK signal as a gated output signal 106 (SYNCH_STBY) having a logical state which depends on the output 106 of the register 104. Hence, the scheme depicted in FIG. 1 is an example of a circuit for isolating a signal (which in this example is the SYSTEM CLOCK signal) in a way that prevents propagation to the SYNCH_STBY signal of “glitches” that may be present on the SYSTEM CLOCK signal when switching to a standby mode (in other words, when the STBY signal goes low).
Unfortunately, in the reduced power mode the SYSTEM CLOCK signal may be inactive, in which case the register 104 will be unable to propagate the asynchronous standby signal 102 to the output 106 of the register 104. In such circumstances, the combinational logic 110 will not isolate the SYSTEM CLOCK signal and thus the SYNCH_STBY signal will be unsuitable for isolating inputs, such as clock, control, and data inputs, to the essential functional blocks, such as a Real Time Clock (RTC). Accordingly, the standby control circuit 100 may not be effective at preventing false activations and deactivations of input signals to the essential functional blocks when the clock signal is inactive which may thus lead to data corruption, unpredictable operation and/or increased power consumption.
It would be advantageous to provide a standby control circuit that is responsive to an asynchronous standby signal irrespective of whether the clock signal is active or inactive. This may be important for integrated circuit modules that provide a reduced power operating mode that disables the clock signal to reduce static power consumption.
It would also be advantageous to provide a standby control circuit that reduces the likelihood of corruption of the timing functions of a real time clock (RTC) during standby mode entry and thus provides for improved robustness and reliability of the RTC.